10-12-2014, 11:38 PM

First of all, thanks to forum member Patrice for sharing a work in progress (His source code for the HP-16C N-Queen's Benchmark).

I have ported this code to the bit commands of the WP-34S which has resulted in doubling the speed of the N-Queens solution over the traditional WP-34S N-Queens benchmark.

Set Wordsize to 32.

Here is the code, starts at memory location 32. I also attach a .dat file so that this code can be loaded into the emulator:

I have ported this code to the bit commands of the WP-34S which has resulted in doubling the speed of the N-Queens solution over the traditional WP-34S N-Queens benchmark.

Set Wordsize to 32.

Here is the code, starts at memory location 32. I also attach a .dat file so that this code can be loaded into the emulator:

Code:

` WP-34S `

============

32 [f] LBL C

33 [f] BASE 16

34 3

35 STO I

36 [h] CLx

37 STO 00 //Count

38 1

39 0

40 1

41 0

42 1

43 0

44 1

45 STO 02 //Queen

46 8

47 STO 01 //Line

48 [h] MASKR->X

49 X~Y //Mask width specifier got pushed onto stack above the mask

50 R Dn //Get rid of it

51 [h] SL 01

52 STO -> I //Mask

53 8

54 [h] X~I

55 X~Y

56 [f] LBL 02 //Byte to be tested is in Y. Bit to test ins in I

57 INC 00 //Count First increment the line counter

58 [h] BS?->I

59 [h] GTO 05

60 [f] LBL 03

61 [h] DSZ I

62 [h] GTO 02

63 X~Y

64 [h] X~I

65 INC 01 //Line

66 [h] DSZ I

67 RCL->I

68 [h] DSZ I

69 RCL->I

70 X~Y

71 [h] X~I

72 X~Y

73 [h] GTO 03

74 [f] LBL 05

75 X~Y

76 [h] X~I

77 RCL 02 //Queen

78 X~Y

79 [h] ISZ I

80 STO->I

81 STO J //Save the rotation count in the "TEST" register

82 R Dn //Get rid of it, and pull the rotation candidate into X

83 [h] RL->J //Rotate by the rotation count. TODO might be better way to do this: RL -> -> I Then could drop two lines above

84 [h] OR

85 DEC 01 //Line. Note: Might be better way to do this like: DSZ

86 RCL 01

87 [f] x=0? //Are we done?

88 [h] GTO 04 //Yes Done: Terminate

89 R Dn //No, Not done

90 RCL 03 //Mask

91 [h] NOT

92 [h] AND

93 [h] RR 09

94 [h] RRC 08

95 [h] RL 16

96 [h] RLC 08

97 [h] RR 07

98 ENTER

99 ENTER

100 ENTER

101 [h] RL 08

102 [h] OR

103 ENTER

104 [h] RL 16

105 [h] OR

106 RCL 03 //Mask

107 [h] AND

108 RCL L

109 [h] XOR

110 [f] X=0?

111 [h] GTO 06

112 [h] OR

113 [h] ISZ I

114 STO->I

115 8

116 [h] X~I

117 X~Y

118 [h] GTO 02

119 [f] LBL 06

120 8

121 STO + 00 //Count. Increment count by 8

122 INC 01 //Line Increment Line count by 1

123 RCL->I

124 [h] DSZ I

125 RCL->I

126 X~Y

127 [h] X~I

128 X~Y

129 [h] GTO 03

130 [f] LBL 04

131 RCL 00 //Count

132 [g] RTN //Solution: 8 4 1 3 6 2 7 5 In every second register above 3